1. Field of the Invention
The present invention relates to a boosted potential generation circuit used for a semiconductor integrated circuit, particularly a semiconductor memory, its control method, and its manufacturing method.
2. Description of the Related Art
Generally, in a semiconductor integrated circuit, particularly a semiconductor memory, an external power supply voltage supplied from an external power source tends to be reduced with an increase of a memory capacity. Further, a recent demand is directed to a higher speed of the semiconductor memory. In order to meet such a demand or a requirement, a boosted potential generation circuit is disposed in the semiconductor memory to boost the external power supply voltage. At this boosted potential generation circuit, the external power supply voltage is boosted to voltage necessary for the semiconductor memory, whereby a higher speed is realized in an internal memory cell.
On the other hand, since the increased memory capacity also brings about an increase of electric current consumption, it is necessary to reduce the electric current consumption. Generally, therefore, boosted potential generation circuits are disposed in a plurality of circuits within the semiconductor memory, and each boosted potential generation circuit is designed in accordance with potential necessary for the circuit. In any case, preferably, the boosted potential generation circuit has small electric current consumption and a small chip occupation area, and can generate various boosted potentials only by simple design changing.
A boosted potential generation circuit of such a conventional type is described in Japanese Patent Application Laid-Open No. 2000-112547 (referred to as a reference 1, hereinafter). The boosted potential generation circuit described therein is used together with a substrate potential generation circuit. The boosted potential generation circuit supplies boosted voltage (VPP) to a word line of a memory array and a peripheral circuit. On the other hand, the substrate potential generation circuit supplies predetermined negative voltage (VBB) to a device substrate. In the case of the reference 1, a constitution is adopted where boosted potential (VPP) generated by the boosted potential generation circuit is supplied to the substrate potential generation circuit to obtain desired voltage from this boosted potential (VPP).
Further, the substrate potential generation circuit described in the reference 1 is constituted of an oscillator such as a ring oscillator for generating clocks, and a charge pump circuit. In this case, at the charge pump circuit, a clock from the oscillator and a clock inversion signal are supplied to a plurality of capacitive elements and a transistor to boost voltage, and control is executed to prevent excessively high boosted potential caused by clamping of a voltage level.
The adoption of the above constitution enables use of a thin transistor of a gate oxide film (referred to as a gate insulating film, hereinafter) as the transistor used for the charge pump circuit. However, the reference 1 explains only the constitution of the substrate potential generation circuit, and discloses nothing concerned with a constitution of the boosted potential generation circuit for generating boosted voltage (VPP) from external voltage (VDD).
On the other hand, Japanese Patent Application Laid-Open No. 297950/1999 (referred to as a reference 2, hereinafter) discloses a semiconductor integrated circuit device where a MOSFET having a thick gate insulating film is disposed in a first internal circuit operated by receiving boosted voltage (VPP) generated by an internal voltage generation section, and a second internal circuit operated by receiving stepped-down voltage (VDL) is constituted of a MOSFET having a thin gate insulating film. However, the reference 2 discloses only the circuit operated by receiving the boosted voltage, but nothing concerned with a constitution of the circuit for generating boosted voltage.
Further, Japanese Patent Application Laid-Open No. 283667/1994 (referred to as a reference 3, hereinafter) presents a high voltage generation circuit used to generate high voltage necessary for deletion or writing of a nonvolatile memory. This presented high voltage generation circuit is provided with a plurality of MOS transistors and boosting capacitive elements connected to mutual connection nodes of these transistors and, as insulating films of the plurality of boosting capacitive elements, films having two or more types of thickness are used. According to the reference 3, it is possible to constitute a high voltage generation circuit having a small pattern area and operated by low voltage.
However, also in the reference 3, nothing is disclosed in connection with requirements and a specific constitution of a boosted voltage generation circuit used for a DRAM.
Now, description will be made of a specific constitution and requirements of the boosted voltage generation circuit generally used for a DRAM.
Recent achievement of a higher density and miniaturization of a memory cell in the DRAM have also brought about a reduction of external power supply voltage VDD, for example from 5V to 2V or about 1.8V Such a reduction of the external power supply voltage to about 1.8V necessitates generation of voltage of 3.0V or higher (i.e., 3.0V to 3.9V) as boosted voltage (VPP) at the boosting circuit of the internal voltage generation circuit.
Conventionally, the boosted voltage generation circuit of the above type used for the DRAM is constituted of an oscillator and a charge pump circuit and, as the charge pump circuit, a double or triple boosted voltage generation circuit is used. Here, it must be kept in mind that the boosting circuit of this type is used not only for supplying boosted potential to the word line but also for supplying boosted potential or overdrive potential to a shared MOS transistor, a bit line precharge MOS transistor, and a sense amplifier, and used as control signals therefor.
However, in the aforementioned constitution of the boosting circuit using the conventional boosted voltage generation circuit, a situation has arisen where various power potentials including the word line boosted voltage (VPP) cannot be supplied sufficiently to the memory array.
Further, in the semiconductor memory, particularly the DRAM, as described above, even if the external power supply voltage is reduced, a transfer gate of the memory cell array and the sense amplifier regarding data transfer are operated by boosted voltage, and a sufficient writing level of the memory cell is secured to carry out an operation at a much higher speed.
In this connection, generally, for the MOS transistor constituting a DRAM memory cell, a MOS transistor having a relatively thick gate insulating film (e.g., 6 nm) which withstands the boosted voltage is used and, for the MOS transistor constituting a peripheral circuit operated by external power supply voltage, a MOS transistor having a thin gate insulating film (e.g., 3.5 nm) is used
Specifically, in the DRAM provided with the word line, the bit line, the memory cell and the sense amplifier, if the sense amplifier is stepped down together with a reduction of the external power supply voltage, an operation speed of the sense amplifier is lowered, and thus the sense amplifier must be operated by boosted voltage. Additionally, in order to carry out precharging of the bit line and a writing operation of the memory cell at a high speed, gate voltage for controlling the operations of these transistors must be boosted. As a result, it is impossible to make thin the gate oxide film of the MOS transistor constituting the memory cell.
On the other hand, the boosted voltage generation circuit for generating various voltages for the DRAM is provided with a capacitor MOS transistor and a transfer MOS transistor. Generally, however, because of application of boosted voltage, these MOS transistors are constituted of MOS transistors having film thickness equal to that of the gate oxide film of the MOS transistor of the memory cell.
Further, as described above, in the case of generating corresponding internal power potentials in various circuits, if the boosted voltage generation circuit for generating double boosted potential from the external power supply voltage, various power potentials including word line boosted potential necessary for the DRAM cannot be generated. For example, as the external power supply voltage is reduced, there is a tendency for requiring supplying of, in addition to the word line boosted potential, potentials for controlling the shared MOS transistor, the bit line precharge MOS transistor, and/or overdriving of the sense amplifier to the boosted potential generation circuit.
Considering the foregoing, from now on, the boosted potential generation circuit may need to generate high boosted potential of 3.0 to 3.9V or higher.
On the other hand, in order to obtain the aforementioned high boosted potential, as in the conventional case, the use of a double boosted potential generation circuit is assumed. First, current efficiency of the boosted potential generation circuit is normally represented by a ratio between load current and current consumption (i.e., load current/current consumption). However, if the double boosted potential circuit is used to generate high voltage, as generated voltage becomes higher, a sharp reduction occurs in current efficiency. As a result, if the double boosted potential generation circuit is used to generate high boosted potential, there is a drawback that a sufficient current supplying capability cannot be obtained because of the impossibility of preventing a reduction in current efficiency. Additionally, in order to obtain a sufficient current supplying capability by using the double boosted potential generation circuit, the capacitor MOS transistor must be enlarged, which consequently increases a chip size.
Under such circumstances, consideration has also been given to the use of the triple boosted potential generation circuit for stably maintaining current efficiency even at high boosted potential. However, in the triple boosted potential generation circuit, since generated voltage itself is high, as a MOS transistor used for the boosted potential generation circuit, a capacitor MOS transistor of a thick gate insulating film must be used to withstand the high voltage. This means that also in the triple boosted potential generation circuit, as a capacitor MOS transistor for obtaining a desired capacitance value, a MOS transistor of a thick gate insulating film must be used.
However, the capacitor MOS transistor having the thick gate insulating film must increase its area in order to realize a desired capacitance value. As a result, there is a drawback that the boosted potential generation circuit cannot be formed by a small area because of a large chip size.
Additionally, as the external power supply voltage is reduced, consideration may also be given to the use of a MOS transistor having a thin gate insulating film used for a peripheral circuit as each of the capacitor MOS transistor and the transfer MOS transistor of the boosted potential generation circuit in accordance with a scaling rule.
However, if the boosted potential generation circuit using the thin transfer MOS transistor is used, since high potential cannot be supplied to the gate insulating film, high boosted potential cannot be obtained. As a result, there is also a drawback that a demand for a higher speed of the semiconductor memory cannot be satisfied because of the impossibility of executing a high-speed operation.
An object of the present invention is to provide a boosted potential generation circuit suitable for a semiconductor memory, which enables generation of not only double boosted potential but also various potentials in accordance with a reduction in external power supply voltage.
An object of the present invention is to provide a boosted potential generation circuit capable of obtaining a large current supplying capability without increasing a chip side, and its control method.
Another object of the present invention is to provide circuitry capable of increasing an achievement level and a current supplying capability while suppressing an increase in current consumption, which can be used for a boosted potential generation circuit.
Yet another object of the present invention is to provide a boosted potential generation circuit of a small area and high efficiency by optimizing a gate insulating film of a MOS transistor.
The other object of the present invention is to provide a control method for optimally driving the aforementioned boosted potential generation circuit.